Xiamen Hejiaxing Electronics Co., Ltd.

HJX-ADRV9029-SDR

With the further development of massive MIMO applications, it brings a greater challenging requirement for power consumption, inter-channel matching and isolation of the system.

ADRV9029 is the fourth generation broadband RF transceiver of ADI. It adopts the latest 28nm process. Compared with the previous generation product (ADRV9009), it improves the integration twice under the same power consumption, then improves the radiodensity to support more antennas. At the same time, it also improves the isolation of chip ports.

ADRV9029 supports frequency division duplex (FDD) and time division duplex (TDD) standards, which can help simplify the design of 3G / 4G / 5G applications while reducing system power, size, weight and cost.

ADRV9029 can be used to support base station applications, including single standard and multi standard 3G / 4G / 5G macro cell base stations, large-scale MIMO (M-MIMO) and small cell systems.

ADRV9029 is the DFE version of ADRV9026, DPD and CFR functions are integrated inside. In the application of wireless base station, 4 channels can save about 7W power consumption for FPGA and also save a lot of FPGA resources.

As a partner of ADI, Xiamen Hejiaxing (HJX) have launched HJX-ADRV9029-SDR in combination with RadioVerseTM technology, which will help customers develop systems with more powerful features and functions than before.

Product Details

1、HJX-ADRV9029-SDR SYSTEM DIAGRAM DESCRIPTION

HJX-ADRV9029-SDR is highly customizable. It can provide wide bandwidth and tuning range for various applications. It includes one ADRV9029 Quad-channel transceiver and one Xilinx Zynq Ultrascale plus MPSOC XCZU11EG. It makes the whole platform obtain powerful data processing ability. Meanwhile, it has a 1GB DDR4 equipped for SoC programming system and has a 512MB DDR4 equipped for SOC programming logic part. It provides great flexibility for the development of custom applications. Besides, it provides 32GB EMMC flash memory for data storage and a Nor Flash 64MB as user flash, and also reserves additional options to start the system via SD card.

For the clock circuit of HJX-ADRV9029-SDR, it select AD9545 as the main clock chip, plus a clock buffer to expand the number of clock channels. Please kindly note that AD954S series chips support synchronous source input, such as GPS second pulse, IEEE1588, etc.

RF front end of HJX-ADRV9029-SDR provides hardware support for ADRV9029 RX QEC, TX QEC and LO Leakage calibration.At the same time, this board provides front LNA to ensure better receiver performance, and also provides a gain block at the transmitter to ensure high output signal power. And since ADRV9029 does not support external LO function yet, only hardware is reserved for internal and external LO circuits on the board. Since the ADRV9029 chip reserved an external LO input pin ( but API does not support the external Lo function at this stage), HJX-ADRV9029-SDR also reserves the hardware circuit of external LO. If in the future the API of ADI can support the function of external LO, the user can develop this part of function by himself.

HJX-ADRV9029-SDR has a wide range of I / O functions and can use various high-speed I / O, including QSFP, TF card, USB2.0, Gigabit Ethernet, power switch, Mini USB downloader and debug port. A 40G QSFP interface was reserved on the hardware board for the customer to further develop high-speed transmission interface for data transportation in the future. Besides, 36 channel- GPIO pins are introduced from HD Bank of FPGA for communication with external modules. Xilinx FPGA Downloader is also integrated, which can easily realize FPGA program download and serial port communication.

HJX-ADRV9029-SDR’s circuit design idea and programming logic makes it easy for customers to evaluate and design. Then it is integrated into the customized carrier seamlessly for further prototype design and shortening the time to market of the final product.

2、HJX-ADRV9029-SDR SYSTEM TECHNICAL SPECIFICATIONS

Specifications	Typ. values
Frequency tuning range	75MHz ~ 6GHz
Max RX bandwidth	200MHz
Max TX bandwidth	450MHz
Max ORX bandwidth	450MHz
Operation mode	TDD/FDD
ADC/DAC accuracy	16bit/14bit
Dimension	184mm*255mm
Working voltage	12V
RF Interface type（MCX）	4xTX ports 4xRX ports 4xORX ports Reference clock input Trigger input PPS input

Note: Select the corresponding balun model according to different application frequency bands. The balun sealed package is 0805. The default balun model of the board is HHM1525.

3、HJX-ADRV9029-SDR INTERFACE SPECIFICATION

a) Input（receiver）: MCX-KE(4pcs);

b) Output ( transmitter): MCX-KE(4pcs);

c) Feedback channel (receiver): MCX-KE(4pcs);

d) External clock input interface: MCX-KE(1pc);

e) External LO input interface: MCX-KE（2pcs）, reserved;

f) Gigabit network port: RJ45（1pc）;

g) SD card connector: Micro SD（1pc）;

h) 100G Optical module interface: QSFP(1pc）;

i) USB-UART interface port &JTAG interface port: Mini-USB（1pc）;

j) Power supply port: VH3.96mm 2pin（1pc）;

k) PHD2.0 connector: 2X10PIN（2pcs）

4、HJX-ADRV9029-SDR TEST DATA

4.1. In-band harmonics

Test condition: Single tone signal mode.The signal is provided by the signal source and output to the spectrum analyzer after passing through the HJX-ADRV9026-SDR development board to observe the spectrum, as shown in the figure below.

帶內(nèi)雜散.png

4.2. Frequency response

9026頻率響應(yīng).png

4.3. Phase noise test

9026相位噪聲.png

4.4.Time delay

Test conditions: CDMA pilot signal mode, signal source input power is -35dbm, after HJX-ADRV9026-SDR development board, output to spectrum analyzer, the total delay tested is 1.38us (including test system delay 0.36us).

9026時(shí)延.png

4.5.ACPR

Test conditions: HJX-ADRV9026-SDR setting conditions, RX local oscillator is set to 2595MHz, TX local oscillator is set to 2595MHz, TX attenuation value is 10dB.Fdd-lte signal mode, the input frequency is set to 2595MHZ, and the input power of signal source is -32.5dbm. After hJX-ADRV9026-SDR development board, the output power to the spectrometer is -3.3dbm.